The present invention refers to a data transfer control unit when doing data transfer between 2 systems which are respectively at operation, for example, under any different CPU, and particularly to an available data transfer control unit when doing serial data transfer.
FIG. 8 shows a block diagram of 2 data transfer control unit each to perform serial data transfer, in which 1, 1a show systems respectively performing their operation under any different CPU; 2 shows a signal line to conduct serial communication between the 2 systems; 3 shows a control line to control said communication.
Besides, 4, 4a show CPUs (central processing units); 5, 5a show ROMs in which is held a program dedicated for reading these systems 1, 1a; 6, 6a show RAM in which CPUs 4, 4a write and read the program and data in operation followed by the program to be held in ROMs 5, 5a; 7, 7a show serial I/O interfaces to perform communication between the systems 1, 1a; 8, 9 show other I/O interfaces to connect peripheral equipment, such as keyboard, CRT, etc. other than said serial I/O interfaces; and 10, 10a show system buses to send out address signals, data signals, and control signals to connect CPUs 4, 4a to a peripheral LSI of said serial I/O interfaces 7, 7a, etc.
Their operation will be exemplified as below: Both systems 1 and 1a are to make stand-alone operation according to the programs which have been held in ROMs 5, 5a.
CPUs 4, 4a load the program from ROMs 5, 5a through the system buses 10, 10a and read/write on RAMs 6, 6a according to its need during execution of the program. In addition, the states of I/O interfaces 8, 9, etc. are to be monitored via the system buses 10, 10a processing in response to each state. When information exchange comes to its need between each system 1 and 1a in a certain state, CPUs 4, 4a will use the serial I/O interfaces 7, 7a.
In case of sending the information from one system to the other system, CPU 4 begins with checking for the feasibility of transmitting from the serial I/O interface 7, and in case of infeasibility, it has to wait for its feasibility. Then, upon informing of sending the signals to the opposite side using the control signals 3, it will command to send out the data to the serial I/O interface 7.
The serial I/O interface 7 receives the command from CPU 4, and outputs the data to the signal line 2.
The serial I/O interface 7a on the other system 1a receives the data, either informs CPU 4a of termination of receiving signals by means of interrupt signals, or stands the internal flag. Upon recognition that CPU 4a receives the data by receiving the interrupt signals or by monitoring the flag status of the serial I/O interface 7a, it reads the information from the system 1 by means of the serial I/O interface 7a, with its need, the information will be held into RAM 6 for its processing.
In case of sending plural data, this is to be repeated. Also the case of sending the data from the system 1a to the system 1 will be done in the same procedure.
The traditional data transfer being done as mentioned above, in case of making the data transfer, CPUs 4, 4a of each system 1, 1a will be unable to dedicate for processing I/O interfaces 8, 9, etc. of each system, resulting in being occupied with large processing time of controlling the serial I/O interfaces 7, 7a for effecting communication between both systems. Thus, in order to perform a large amount of data information exchange, there have been such problematic points that load of host CPU is large to the extent that any larger processing capability is to be required than for CPUs 4, 4a.